Architecture of a Microcontroller

1Purpose and structure of the course6 min

The answer passes through four layers. The first is the representation of information - the way a real-world quantity becomes a string of zeros and ones. The second is memory - the place where those strings sit and wait. The third is the central processing unit - the machine that reads them, transforms them and writes them back. The fourth is the clock - the periodic signal that gives all these operations their rhythm.

Learning outcomes

• Convert a value between binary, decimal and hexadecimal, and identify the active bits
• Distinguish control registers from status registers, and drive a pin through registers
• Compare SRAM, Flash and EEPROM by volatility, granularity and write cycles
• Explain the role of the flags in SREG and the mechanism of stack overflow
• Compare the von Neumann architecture with Harvard and explain the AVR's two-stage pipeline
• Calculate the number of instructions per second and the SRAM available for an application

2The bit, the byte and the three notations10 min

A microcontroller does not know what a number, a letter or a temperature is. All it knows is that at a given point in the circuit the voltage is close to the supply or close to ground - this binary choice is the only elementary information the hardware can hold unambiguously, and it is called a bit.

The fundamental group of eight bits is called a byte - 2⁸ = 256 distinct values, enough for the Latin alphabet (ASCII) and exactly the usual resolution of a simple ADC. Multiples form in powers of two: 1 KB = 1024 bytes, not 1000.

Three notations for the same value

3Registers and special function registers11 min

A register is a very high-speed memory cell, built right inside the central unit or a peripheral module, to which the processor has immediate access - built from flip-flops placed next to the arithmetic unit, so that reading or writing does not require a bus cycle. Precisely because they are expensive in silicon area, registers are few, while memory is cheap and abundant.

By function, registers fall into four families: data (operands and results), address (on AVR, the X, Y, Z register pairs allow traversing an array with automatic increment), control (settings that determine the behavior of a module) and status (report conditions).

Special function registers (SFR)

These are not storage locations, but interfaces - each is wired physically to a concrete internal circuit. On the ATmega328P, each port is served by three registers: DDRx (direction: 1=output, 0=input), PORTx (the output level, or enabling the pull-up for input) and PINx (reading the real electrical state).

DDRB |= (1 << PB5);   /* PB5 becomes an output */
DDRD &= ~(1 << PD2);  /* PD2 becomes an input */
PORTD |= (1 << PD2);  /* enable the internal pull-up on PD2 */

PORTB |= (1 << PB5);  /* turn on the LED */
PORTB &= ~(1 << PB5); /* turn off the LED */
PORTB ^= (1 << PB5);  /* toggle the LED state */

if ((PIND & (1 << PD2)) == 0) {   /* button pressed = level 0 */
    PORTB |= (1 << PB5);
}

(1 « PB5) builds a mask: 0b00100000. |= performs a bitwise OR - bit 5 becomes 1, the rest stay untouched. &= with the mask negated by ~ performs an AND with 0b11011111 - bit 5 becomes 0, the rest untouched. ^= performs an EXCLUSIVE-OR, which flips exactly the bit covered by the mask.

4The memory of a microcontroller11 min

Memory is divided, by purpose, into program memory (the instructions, which must survive a power interruption) and data memory (variables, intermediate results, the stack - permanently modified, may be volatile).

Volatile memories

SRAM (static RAM) uses a cell of 4-6 transistors, wired as two inverters in a loop - the loop sustains itself as long as power is present, so it needs no refreshing and works at high speeds. The price: an SRAM cell takes up several times more silicon than a DRAM one, which is why it is used where speed matters and quantity is small - the cache memory of processors and the data memory of microcontrollers. DRAM uses a capacitor and a transistor - the cell is small (cheap per bit), but the charge leaks away, so the content must be refreshed periodically by a dedicated controller; it is the type used for the main memory of computers.

Non-volatile memories

Flash memory is non-volatile and electrically reprogrammable, but erasing cannot be done on individual locations, only on entire blocks (pages) - which is why erasing is said to be non-selective. It does support a large number of cycles (on the order of tens of thousands for program memories), which is why most current microcontrollers use it to store the program: it allows in-circuit reprogramming, hence updating the firmware of a product already shipped.

5The central unit: ALU, SREG, the stack12 min

The central processing unit (CPU) fetches instructions from memory, interprets them and executes them, generating the signals that drive the rest of the circuit. It splits into the arithmetic and logic unit (ALU) and the control unit.

The ALU and the general registers

The ALU takes one or two operands and an operation code as input, produces a result and a set of flags. There are few, elementary operations: add, subtract, compare, AND, OR, EXCLUSIVE-OR, negate, shift, increment, decrement - everything that counts as complicated computation is built from these, through the program.

The status register (SREG)

On every arithmetic operation, the ALU updates SREG, whose bits are called flags: Z (zero), C (carry - carry out of the most significant bit), N (negative - copies the sign bit), V (signed overflow), S (corrected sign, N⊕V), H (half-carry between nibbles), T (general-purpose bit), I (global interrupt enable - if it is not 1, no interrupt is taken into account).

The control unit and the stack

The program counter (PC) holds the address of the next instruction - it increments automatically after each fetch; jumps and calls work by writing a new value into the PC, the only branching mechanism.

6Buses, von Neumann and Harvard11 min

The central unit communicates with memory and peripherals through buses: address (unidirectional, determines the maximum addressable capacity - a bus of n lines addresses 2ⁿ locations), data (bidirectional, its width gives the architecture its name - "8-bit" means an internal 8-bit data bus) and control (read/write commands, clock, interrupts).

von Neumann versus Harvard

In von Neumann, a single shared memory for data and instructions, a single bus. Execution requires at least two stages (fetch+decode, then execute), and the two accesses crowd onto the same path - a phenomenon called the von Neumann bottleneck. Advantage: flexibility - the program can modify its own code.

In Harvard, the memory spaces for instructions and data are physically separate, each with its own bus - fetching an instruction and accessing a data item can happen simultaneously.

Pipeline and hazards

The idea of overlapping execution stages is called a pipeline, by analogy with an assembly line - several instructions are simultaneously in progress, each at a different stage.

Situations that stall the line are called hazards: data hazards (an instruction needs the result of an earlier, unfinished one), control hazards (at branches, the outcome of the condition is not known when the next instruction has already been fetched - if the branch is taken, the instructions fetched for nothing are discarded) and structural hazards (two instructions need the same resource at the same time).

7The instruction set: RISC versus CISC8 min

The instruction set is the collection of basic commands a microcontroller understands - defined in silicon, through the structure of the decoder, and it forms the boundary between hardware and software.

RISC versus CISC

A RISC processor recognizes a small, uniform set of operations; complicated operations are obtained by combining them, so a RISC program is longer in instruction count - but the instructions, simple and of the same size, decode quickly and mostly execute in a single cycle. This makes execution predictable, essential in real-time systems.

A CISC processor has a rich set (over eighty instructions), many specialized, differing in format and duration - a CISC program is shorter, an advantage when memory was expensive, but the duration of each instruction varies and decoding is complicated.

8ATmega328P architecture10 min

The ATmega328P uses a modified Harvard architecture: the program and data spaces are separate, as in Harvard, but there is a path (the LPM instruction, the Z register) through which the central unit can read constants from program memory - without it, a table of constants would need to be copied into SRAM at startup, needlessly consuming a scarce resource.

Three memories, with distinct roles: Flash of 32 KB (16384 words of 16 bits, so the PC has exactly 14 bits), split into an application section and a bootloader section (a few hundred bytes, receives the new program over the serial port); SRAM of 2 KB, with a unified address space (32 general registers, then 64 I/O registers, then 160 extended I/O registers, only then the actual SRAM - which is why PORTB behaves in C like an ordinary variable); and EEPROM of 1 KB, with a separate address space, accessed through three dedicated registers.

9The oscillator circuit and the instruction cycle11 min

Without the clock signal, the microcontroller is not broken, it freezes: the PC no longer advances, instructions are no longer fetched. A microcontroller whose clock has stopped draws very little current - the principle behind power-saving modes.

A quartz crystal oscillates at its own mechanical resonance frequency (piezoelectric effect), determined by its dimensions - not by voltage or temperature, hence extremely stable. The ATmega328P has an internal 8 MHz RC oscillator, factory-calibrated, divided by eight by default (starts at 1 MHz unless told otherwise); the clock source is selected through permanent configuration bits (fuses).

10Powering the microcontroller8 min

The ATmega328P accepts a wide supply range, roughly 1.8-5.5 V - but the voltage range and the maximum frequency are linked: transistors switch more slowly at low voltage, so at 16 MHz the chip needs at least ~4.5 V, and at 1.8 V the guaranteed maximum frequency drops to a few megahertz. Powering it at 3.3 V while clocking it at 16 MHz is a deviation from the specification that can work on the lab bench and fail at extreme temperatures.

A practical rule with no exceptions: one 100 nF ceramic capacitor at every VCC-GND pair, as close as possible to the chip's pins, plus a ~10 µF electrolytic at the board's power input, for slower variations. On the ATmega328P the rule applies to both the VCC-GND pair and AVCC-GND (the analog part); the AREF pin also needs its own capacitor, because noise on the reference voltage shows up directly in the analog-to-digital conversion result.

11A wiring example6 min

What must be connected to an ATmega328P straight out of the bag for it to work? The answer is surprisingly short: a stabilized power supply and a clock source. The rest of the pins serve the application, not the chip itself.

The minimal setup: 5 V supply on VCC/AVCC, ground on GND, 100 nF decoupling capacitors near each pair; a clock source (a 16 MHz crystal with two ~22 pF load capacitors, or nothing if the internal oscillator is used); the RESET pin, active low, held at the supply through a ~10 kΩ pull-up resistor (left floating, it picks up noise and causes random resets); and, if the ADC is used, its own decoupling capacitor on AREF.

int main(void)
{
    DDRB |= (1 << PB5);   /* PB5 configured as an output */
    while (1) {
        PORTB ^= (1 << PB5);           /* toggle the pin state */
        for (volatile long i = 0; i < 200000L; i++) {
            ; /* approximate delay, through an empty loop */
        }
    }
    return 0;
}

12Frequent mistakes4 min

• "PORTB = 0b00100000; is equivalent to PORTB |= (1 << PB5);, just clearer." False - the first form rewrites all eight bits, turning off anything else that was on that port. The effect appears only after weeks, when the port also drives other peripherals. Always modify only the desired bit (|=, &=~, ^=), except during complete initialization.
• "32 KB of Flash is the real limit of an AVR application." Almost never - compiled code is dense and fits comfortably in Flash. The real constraint is the 2 KB of SRAM, quickly exhausted by arrays, buffers and the stack. Check the SRAM usage report after every compile, not just Flash.
• "Without a decoupling capacitor, the setup works anyway - I tested it on the bench." Working on the lab bench guarantees nothing - the effects of missing decoupling are intermittent and typically show up at different temperature, vibration or electrical load. Always place 100 nF as close as possible to every VCC-GND pair, no exceptions.

13Summary and glossary5 min

The elementary piece of information is the bit; eight bits form a byte, written equivalently in binary, decimal or hexadecimal - the last being the data-sheet convention, for the exact correspondence with groups of four bits. Registers are fast memory cells next to the central unit; special function registers are the interfaces through which the program directly commands peripherals, with the essential distinction control (written by the program) / status (written by the hardware). SRAM is volatile and fast, Flash and EEPROM are non-volatile but with limited write cycles. The central unit contains the ALU (with the SREG status register) and the control unit (with the program counter and the stack, whose overflow produces chaotic behavior that is hard to diagnose). The Harvard architecture, with separate buses for program and data, allows the AVR's two-stage pipeline and the execution of most instructions in a single cycle - which is why AVR is RISC. The ATmega328P has 32 KB Flash, 2 KB SRAM (the real constraint) and 1 KB EEPROM. The accuracy of the clock source matters critically for asynchronous serial communication, and decoupling capacitors are not optional.

14Self-check questions6 min

1. The value of a register is 0x6D. Write it in binary and decimal and state the active bits.
2. What is the functional difference between a control register and a status register?
3. Why does the Harvard architecture allow most AVR instructions to execute in a single cycle, unlike von Neumann?
4. What is a control hazard, and how does it explain the variable duration of a conditional branch on AVR?
5. Compare SRAM, Flash and EEPROM by volatility, erase granularity and the number of write cycles.
6. An ATmega328P is clocked at 8 MHz. Calculate the clock period and the approximate number of instructions per second.
7. Explain, starting from u = L·di/dt, why the absence of decoupling capacitors produces seemingly random resets.

15Directions for further study2 min

The next lecture moves from the internal structure to the actual programming process: the toolchain, from source code to the bits in Flash, the Intel HEX format, the structure of Flash memory with the bootloader, and the programming modes (ISP, through the bootloader).

The registers, bits and wiring diagram from this lecture become a real setup in Laboratory 01B, the preparatory lab dedicated to working directly with bits and registers.